B = 2N-1 BECAUSE EACH INPUT AFFECTS HALF THE ROWS

11. - SOLUTIONS
SOLUTIONS

11.7 H = 2

m

. B = 2

n-1

because each input affects half the rows. For a conservative esti-

mate, assume that the decoder consists of an n-input NAND gate followed by a

string of inverters. The path logical effort is thus G = (n+2)/3, so the path effort is

F = GBH = 2

n+m

(n+2)/6. The best numer of stages is N = log

4

F ~ (n+m)/2. The

parasitic delay of the n-input NAND and N-1 inverters is P = n + (N-1). Hence,

the path delay can be estimated as D = ((n+m)/2) (2

n+m

(n+2)/6)^(2/(n+m)) + n +

(N-1)