13 THE ROM CELL IS SMALLER THAN THE SRAM CELL

11.13 The ROM cell is smaller than the SRAM cell. It presents one unit of capacitance

for the transistor. Assume the wire capacitance is 1/2 as much, so each cell pre-

sents 1.5C on the wordline. It has only a single transistor in the pulldown path on

the bitline so the resistance is R. Hence, the logical effort is 1/2, as compared to 2

for the SRAM cell.

The bitline has a capacitance of C/2 from the half contact. If the wire capacitance

is again C/2, the total bitline capacitance is 2

C. Because the cell has a resistance

R, the delay is 2

RC and the parasitic delay is 2

/3.

The ROM can use the same decoder as the SRAM, with a logical effort of (n+2)/3

and parasitic delay of n. Assume the bitline drives a load equal to that seen by the

address so the path electrical effort is H = 1.

Putting this all together, the path effort is F = GBH = 2

(n+2)/6. The path para-

sitic delay is n + 2

/3. The path delay is D = 2N + 4log

[(n+2)/6] + n + 2

/3.

Your modeling and loading assumptions may vary somewhat. The assumptions

about wire capacitance have a large effect on the model.

Chapter 12