3 [ADMITTEDLY, THIS EXERCISE MAY REQUIRE SOME KNOWLEDGE OF CHAPTER 1...

8.3 [Admittedly, this exercise may require some knowledge of Chapter 11 although the

design we use has been presented in Chapter 7. A detailed design is possible with a

simulator and process files, but it’s OK to just capture the basic principles.]

If we summarize the attributes we need for a control RAM cell for an FPGA, we

would like it to be small. In addition, as the RAM cells are dispersed across the chip,

it probably would be advisable to design a cell with the lowest wiring overhead.

Finally, we want a circuit that is robust and easy to use in an FPGA.

A conventional RAM cell was a write line, a read line and data and complement

data lines. Data is read or written using the data lines. To read the RAM cell fairly

complicated sense amplifiers are required and there is normally a complicated pre-

charge and timing sequence required to read the cell (Section 11.2.1). We would

prefer a RAM cell that operated with full logic levels.

A single-ended RAM cell that is often used as a register cell is probably the best

choice. A typical circuit is shown in Figure 7.17j. This circuit has a single ports for

data-in, data-out, write and read. In addition, all signals are full logic levels with the

exception of the data-out signal which has to be held high with a pMOS load (or

precharged and then read). This is probably OK as the global read operation is only

used for testing or to infrequently read out the control RAM contents. It does not

have to be fast.

Design starts with the write operation. The switching point of the “input” inverter

is a balance between the write zero and one operations. This is achieved by using a

single nMOS pass transistor to overwrite a pair of asymmetric inverters. When try-

ing to write a zero, the driving inverter n-transistor and the memory cell write n-

transistor have to overcome the p-transistor pullup of the feedback inverter in the

memory cell. The circuit is shown below. We can arbitrarily size the weak-feedback

inverter so that the pull down circuit triggers the input inverter.

weak feedback inverterdata out (bar)write pass transistordata inreadwritedriver inverter(not in memory cell)ram cellthis inverter is a Lo-Skewinverter so that it’s threshold islower than normal

Figure E8.2 – Write Zero operation for single-ended RAM cell

Writing a one is somewhat constrained by the fact that the write n-transistor can

only pull up to a threshold below V

_DD

(V

_DD

-V

_tn

). This means that the trip point for

the RAM inverter has to be set well below this. This is achieved by having a LO-

skewed inverter (Section 2.5.2). This involves sizing the n-transistor in the inverter

up until the input switch point is comfortably below the V

_DD

-V

_tn

voltage.

Once the cell can be written, the read operation may be considered. If we use a

pMOS load in what is effectively a two input pseudo-nMOS NAND gate or one

leg of a multiplexer, the n-transistor pull-downs have to be able to pull the output to

near zero when both transistors are turned on. Assuming the pulldown n-transistors

are minimum size, this involves lengthening the pMOS pullup until acceptable

operation over voltage, temperature and process are achieved.