A 10-INPUT NAND GATE HAS A LOGICAL EFFORT OF 12/3, SO ESTI-MATE THAT THE PATH LOGICAL EFFORT IS ABOUT 4

11.5 (a) B = 512. H = 20. A 10-input NAND gate has a logical effort of 12/3, so esti-

mate that the path logical effort is about 4. Hence F = GBH = 40960. The best

number of stages is log

F = 7.66, so try an 8-stage design: NAND3-INV-

NAND2-INV-NAND2-INV-INV-INV. This design has an actual logical effort

of G = (5/3) * (4/3) * (4/3) = 2.96, so the actual path effort is 30340. The path par-

asitic delay is P = 3 + 1 + 2 + 1 + 2 + 1 + 1 + 1 = 12. D = NF

+ P = 41.1 τ.

(b) The best number of stages for a domino path is typically comparable to the best

number for a static path because both the best stage effort and the path effort

decrease for domino. Using the same design, the footless domino path has a path

logical effort of G = 1 * (5/6) * (2/3) * (5/6) * (2/3) * (5/6) * (1/3) * (5/6) = 0.060 and

a path effort of F = 610. The path parasitic delay is P = 4/3 + 5/6 + 3/3 + 5/6 + 3/

3 + 5/6 + 1/3 + 5/6 = 7. D = NF

+ P = 24.8 τ.