8.1 Selection of a gate array cell comes down to selecting the number of transistors to place
in series in a cell, remembering that if a cell uses less transistors, then the extra tran-
sistors are not utilized. We can categorize individual gates by the number of series
transistors they require (i.e. an n-strip below a p-strip, as in Figure 8.28). The fol-
lowing table summarizes the usage in particular chip in the exercise:
Cell Type Series transistors Circuit Percentage
D-latch 5 Figure 7.17f with
clock inverter
D-flipflop 10 Two D-latches
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