6%AGEBASED ON THIS ANALYSIS, A THREE SERIES TRANSISTOR GATE ARRAY LO...

6.6%

age

Based on this analysis, a three series transistor gate array looks the lowest area.Note

that it does not have the best utilization (lowest area wasted), but three series tran-

sistors are denser than two because there is less space between transistors.

If we use a Sea-of-gates structure, the pitch is 8 λ but each gate has an extra series

transistor (in general) to isolate the gate. This the table looks as follows:

Sea-of-gates

Cell Total Cells Area Used Area Wasted

DFF 300*16 = 4800 4800*8 = 38400 300*8=2400

4 input gates 100*5 500*8=4000 100*8 = 800

3 input gates 100*4 400*8=3200 100*8 = 800

2 input gates 400*3 1200*8=9600 400*8 = 3200

Total Area 55200 7200

Percentage Wast-

13%

This is close to the 3-input case, but takes the guesswork out of estimating gate

mixes. This is the reason SOG is widely used. In the end, this problem is looking for

some reasoning why one cell size is better than another. Any well reasoned argu-

ment is probably acceptable.