15-16 Allowing for input
Scannable
30
multiplexer
D-flipflop
4 input gate 4 10
3 input gate 3 10
2 input gate 2 40
buffers various 10
Clearly if we were to center on a D-flop, and use a five series transistor cell, at least
60% of the gates would waste transistors (2,3,4 input gates). As an aside, a scannable
D-register would need three blocks if they were 5 transistor series blocks.
While we can guess, a little bit of analysis might help. The pitch of a contacted tran-
sistor is 8λ (Exercise 3.7). (However see Exercise 8.5 where this gets blown out to
14λ if interior poly-contacts are required. For this exercise we’ll stick with 8λ.) A
break in the active area adds 3λ (Table 3.2 Rule 2.2). So the pitch of various gate
arrays is as follows:
Series Transistors Pitch
2 2*8+3 19
3 3*8+3 27
4 4*8+3 35
5 5*8+3 43
We can construct a table as follows that charts usage per 1000 gates. A scannable D
flipflip is assumed to use 15 series transistors. We ignore buffers.
5 series transistors
Cell Total
Area Used Area
Cell
Waste
s
d
DFF 3*300=900 900*43 0
4 input gates 100 100*43 100*8
3 input gates 100 100*43 100*16
2 input gates 400 400*43 400*24
Total Area 64500 12000
Percentage Wast-
Bạn đang xem 15- - SOLUTIONS
