WHICH OF THE FOLLOWING IS A DISADVANTAGE OF USING HIGH-LEVEL METAL...

19. - VLSI DESIGN COURSE LECTURE NOTES EXAM EXAMPLE

VLSI DESIGN COURSE LECTURE NOTES EXAM EXAMPLE

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19. Which of the following is a disadvantage of using high-level metals within primitive cells?

A) higher transistor packing density

B) more metal layers needed for complete chip layout

C) less chip area required for routing

D) less resistance between cells