WHICH OF THE FOLLOWING IS A LAYOUT LAYER IN AN N-WELL CMOS PROCESS

12. - VLSI DESIGN COURSE LECTURE NOTES EXAM EXAMPLE
VLSI DESIGN COURSE LECTURE NOTES EXAM EXAMPLE

12. Which of the following is a layout layer in an n-well CMOS process?

A) n-type substrate

B) contact

C) p-well

D) transistor gate