8 THE VERTICAL PITCH IS DIVIDED INTO THREE BASIC SEGMENTS. FIRST, WE...

3.8 The vertical pitch is divided into three basic segments. First, we have to determine

the spacing of the n-transistor to the GND bus. The next segment is defined by the

n-transistor to p-transistor spacing. Finally, the p-transistor to V

bus spacing

needs to be determined. (all spacings are center to center).

N-transistor to GND bus

First let us assume minimum metal1 widths. Next, the width of a metal contact is

equal to the contact width plus twice the overlap of the metal over the contact = 2 +

2*1 = 4 λ. The minimum width of a transistor is the contact width plus 2*active

overlap of contact = 2 + 2*1 = 4 λ (actually the same as a metal1 contact). So the

spacing of the n-transistor to the GND bus will be half the GND bus width plus

metal spacing plus half of the metal contact width = 0.5*3 + 3 + 0.5*4 = 6.5 λ .

N-transistor to P-transistor spacing

There are two cases: with a polysilicon contact to the gate and without. With the

metal-to-polysilicon contact, the spacing will probably be half of the n-transistor

width plus the metal space plus the polysilicon contact width plus the metal space

plus half the p-transistor width = 0.5*4 + 3 + 4 + 3 + 0.5*4 = 14 λ. The spacing with-

out a contact is half the n-transistor width plus n-active to p-active spacing plus half

the p-transistor width = 0.5*4 + 4 + 0.5*4 = 8 λ. However, the n-well must surround

the pMOS transistor by 6 and be 6 away from the nMOS. This sets a minimum

pitch of 0.5*4 + 6 + 6 + 0.5*4 = 16 for both cases.

P-transistor to V

bus

By symmetry, this is also 6.5 λ.

Summary

The total pitch is 2*6.5 + 16 = 29 λ. The total height of the inverter is 35 λ including

the complete supply lines and spacing to an adjacent cell. In the case where the V

and GND busses are not minimum pitch, the vertical pitch and cell height increase

appropriately.

In this inverter the substrate connections have not been included. They could be

included in the horizontal plane so that the vertical pitch is not affected. If they are

included under the metal power busses, the spacing on the transistors to the power

busses may be altered. Normally, this is what is done the power bus can be sized up

to account for the spacing. This helps power distribution and does not affect the

pitch much.

In an SOI process, if the n to p spacing is 2 λ rather than 12 λ, the pitches are 2*6.5

+ 14 = 27 λ and 2 * 6.5 + 6 = 19 λ respectively for interior poly connection and not.

In older standard cell families (two and three level metal processes), the polysilicon

contact was often eliminated and the contact to the gate was made above or below

the cell in the routing channels. With modern standard cells, all connections to the

cells are normally completed within the cell (up to metal2).