42 WHEN THE CLOCK IS LOW, THE TWO OUTPUTS EQUALIZE AT VDD/2. WHEN TH...

6.42 When the clock is low, the two outputs equalize at V

/2. When the clock rises,

one side pulls down, fully turning ON the pMOS transistor to pull the other side

up. This gate saves precharge power relative to dynamic logic because the precharge

equalizes the two outputs rather than drawing power from the rail. The partial

swing may lead to faster transistions. However, it consumes extra power early in

evaluation because of contention between the partially ON pMOS transistor and

the ON pulldown stack.

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Y / Y